This invention relates to a binary updown counter, and more particularly to a pipeline counter with a reduced number of logic operations that can be implemented with regular, simple, expandable and, therefore, suitable architecture for very large scale integrated circuit (VLSI) implementation.
Large binary updown counters are widely used in digital circuits. Examples include the controller design of a servomotor or the correlator part of very long baseline interferometry. Shown in FIG. 1 is a typical prior-art VLSI design of an up counter which may be used as a model for an updown counter. A single one-bit register labeled R and half adder labeled H is required for each stage (order). The pulses to be counted are applied to the sum input terminal(s) of the half adder for the least significant stage of the counter. The true output (1) of the register is applied to the other input terminal of the half adder through a delay element D. The carry output (C) of the half adder is applied to the sum input of the next stage of higher order.
Such a counter may be readily expanded by replicating the one-bit stage. To adapt that design for an updown counter, only two one bit registers and a half adder are needed in each stage of an n-bit counter, and its expansion to more bits is very easy and straight forward. However, for it to be adapted to also counting down, a fixed value (bias) is added to the sum. Therefore, the sum "zero" represents the middle value of the range of the counter, and the smallest negative number is represented by "zero." Also, it takes n clock times to perform one counting operation in the worst case because of the ripple-carry feature.
To avoid the ripple-carry time for faster counting, it has been common to apply the input pulses simultaneously to all stages through AND gates, but the number of inputs to each gate increases as the size of the counter is increased. And of even more significance is the fact that each stage is different so that expansion by mere replication is no longer possible.